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Samsung successfully builds a 3nm chip with brand new transistors: faster, more economical, denser
Samsung Announces Prototype 256 Mbit SRAM Array Using 3nm Process Technology and All-New MBCFET Transistors. The sample made it possible to confirm the characteristics of the future technical process. Thus, Samsung has stepped from theory to practice and it can be expected that it will launch 3-nm semiconductor production next year.
Evolution of transistors. Image source: Samsung
It should be said that the abbreviation MBCFET (multi-bridge channel FET) in the name of a new type of transistor is a registered trademark of Samsung. In a broad sense, these are the so-called GAAFET transistors with a ring or all-encompassing gate, when a channel or several channels of a transistor are surrounded by a gate on all four sides.
This concept was introduced back in 1988 and has been well studied theoretically, but the reason to switch to this structure appeared only now, since the classic FinFET transistors with vertical fins cease to work normally with technological standards less than 5 nm. In the case of a further increase in productivity and a decrease in consumption with a simultaneous decrease in the physical size of transistors (in the process of decreasing technological standards), it becomes more difficult to manage transistor channels. Therefore, increasing the contact area between the gate and the channel due to the full coverage of the channel is a simple way out of the situation, which, which is very important, allows the production of new transistors on the same equipment.
Image source: Samsung
Add, an important innovation in the production of chips on MBCFET (GAAFET) transistors will be the ability to set the width of the nano-page channels, as well as their number in each transistor, for each individual case. For example, for more efficient logic, the width of nanopages can be increased, and for blocks with low consumption, it can be decreased.
Moreover, it becomes possible to design so flexibly that even in a single six-transistor SRAM unit cell, part of the transistors can be created with wide nano-channel channels, and some with narrow. This is exactly what Samsung demonstrated with its prototype 256Mb 3nm SRAM array. Measurements showed that switching to a cell with mixed transistors out of the blue reduced the write voltage by 256 mV.
Controlling the width of nanopage channels is easier than adding new edges in FinFETs. Image source: Samsung
Finally, the company has proven its ability to achieve new levels of productivity and efficiency. So, in comparison with the 7nm 7LPP process technology, the operating speed of 3nm MBCFET transistors increased to 30% (with the same level of consumption and complexity), and when operating at the same frequencies and the same complexity, the consumption decreased to 50%. The increase in the density of transistors in a mixed circuit (SRAM plus logic) was up to 80%.